The tradeoff between CMOS logic and emitter-coupled logic (ECL) is well understood. CMOS is very good for low to mid-range frequencies because at these frequencies power consumption is low. In addition, the area required for CMOS logic is extremely small. However, as the frequency of an associated clock increases, static CMOS logic design becomes very noisy and requires large amounts of power. At some point it becomes desirable to perform higher frequency operations using ECL. In contrast, the power consumption of an ECL cell is independent of frequency. However, ECL is expensive in terms of silicon die area. Hence, it is common to perform higher frequency logic operations using ECL and lower frequency logic operations using CMOS logic.
Utilization of both of these technologies requires conversion between a high frequency master ECL clock and a high frequency CMOS clock. Such a high frequency CMOS clock may be used as a clock for a state machine that generates slower logic clock signals. This conversion conventionally creates several problems. First, extremely high power is required to generate the conversion. This required power can counteract the power consumption savings of using a mix of ECL and CMOS logic. Such a mix is commonly referred to as mixed mode logic. In addition, the conversion conventionally places a high dependance on the power supply. Furthermore, if the latency period of the conversion, or transport delay, is too long, logic will no longer be synchronously clocked, creating additional clocking problems. In addition, a phenomena known as jitter affects ECL to CMOS converters. Jitter refers to small variations about a common level of a signal, such as a clock signal. Short transport delay and low jitter are desirable attributes of an ECL to CMOS logic converter.